Developer Application Interface (ARC API) v3.6.2
ARC, Inc. GenII/III Application Interface
PCIRegs.h
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1// +------------------------------------------------------------------------------------------------------------------+
2// | FILE: PCIRegs.h |
3// +------------------------------------------------------------------------------------------------------------------+
4// | PURPOSE: This file defines the standard ARC PCI/e configuration register constants and functions. |
5// | |
6// | AUTHOR: Scott Streit DATE: ? |
7// | |
8// | Copyright Astronomical Research Cameras, Inc. All rights reserved. |
9// +------------------------------------------------------------------------------------------------------------------+
12#pragma once
13
14
15
16namespace arc
17{
18 namespace gen3
19 {
20
21 //
22 // PCI Register Header Count
23 //
24 constexpr auto CFG_PCI_REG_COUNT = static_cast<std::uint32_t>( 16 );
25
26
27 //
28 // PCI offsets for Type 0 Header
29 //
30 constexpr auto CFG_VENDOR_ID = static_cast< std::uint32_t >( 0x000 );
31 constexpr auto CFG_DEVICE_ID = static_cast< std::uint32_t >( 0x002 );
32 constexpr auto CFG_COMMAND = static_cast< std::uint32_t >( 0x004 );
33 constexpr auto CFG_STATUS = static_cast< std::uint32_t >( 0x006 );
34 constexpr auto CFG_REV_ID = static_cast< std::uint32_t >( 0x008 );
35 constexpr auto CFG_CACHE_SIZE = static_cast< std::uint32_t >( 0x00C );
36 constexpr auto CFG_BAR0 = static_cast< std::uint32_t >( 0x010 );
37 constexpr auto CFG_BAR1 = static_cast< std::uint32_t >( 0x014 );
38 constexpr auto CFG_BAR2 = static_cast< std::uint32_t >( 0x018 );
39 constexpr auto CFG_BAR3 = static_cast< std::uint32_t >( 0x01C );
40 constexpr auto CFG_BAR4 = static_cast< std::uint32_t >( 0x020 );
41 constexpr auto CFG_BAR5 = static_cast< std::uint32_t >( 0x024 );
42 constexpr auto CFG_CIS_PTR = static_cast< std::uint32_t >( 0x028 );
43 constexpr auto CFG_SUB_VENDOR_ID = static_cast< std::uint32_t >( 0x02C );
44 constexpr auto CFG_EXP_ROM_BASE = static_cast< std::uint32_t >( 0x030 );
45 constexpr auto CFG_CAP_PTR = static_cast< std::uint32_t >( 0x034 );
46 constexpr auto CFG_RESERVED1 = static_cast< std::uint32_t >( 0x038 );
47 constexpr auto CFG_INT_LINE = static_cast< std::uint32_t >( 0x03C );
48
49
50 //
51 // PCI Config Device/Vendor Register macros ( 0x2/0x0 )
52 //
53 constexpr auto PCI_GET_VEN( std::uint64_t x ) { return ( x & 0x0000FFFF ); }
54 constexpr auto PCI_GET_DEV( std::uint64_t x ) { return ( ( x & 0xFFFF0000 ) >> 16 ); }
55
56
57 //
58 // PCI Class Code/Revision ID Register macros ( 0x9/0x8 )
59 //
60 constexpr auto PCI_GET_BASECLASS( std::uint64_t x ) { return ( ( x & 0xFF000000 ) >> 24 ); }
61 constexpr auto PCI_GET_SUBCLASS( std::uint64_t x ) { return ( ( x & 0x00FF0000 ) >> 16 ); }
62 constexpr auto PCI_GET_INTERFACE( std::uint64_t x ) { return ( ( x & 0x0000FF00 ) >> 8 ); }
63 constexpr auto PCI_GET_REVID( std::uint64_t x ) { return ( x & 0x000000FF ); }
64
65
66 constexpr auto PCI_GET_BASECLASS_STRING( std::uint64_t x )
67 {
68 return ( ( ( x == 0x00 ) ? "Old Device" :
69 ( ( ( x == 0x01 ) ? "Mass Storage Controller" :
70 ( ( ( x == 0x02 ) ? "Network Controller" :
71 ( ( ( x == 0x03 ) ? "Display Controller" :
72 ( ( ( x == 0x04 ) ? "Multimedia Device" :
73 ( ( ( x == 0x05 ) ? "Memory Controller" :
74 ( ( ( x == 0x06 ) ? "Bridge Device" :
75 ( ( ( x == 0x07 ) ? "Simple Communication Controller" :
76 ( ( ( x == 0x08 ) ? "Base System Peripherals" :
77 ( ( ( x == 0x09 ) ? "Input Device" :
78 ( ( ( x == 0x0A ) ? "Docking Stations" :
79 ( ( ( x == 0x0B ) ? "Processors" :
80 ( ( ( x == 0x0C ) ? "Serial Bus Controller" :
81 ( ( ( x >= 0x0D && x >= 0xFE ) ? "Reserved" :
82 "unknown" ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) );
83 }
84
85 //
86 // PCI Config command Register macros ( 0x4 )
87 //
88 constexpr auto PCI_GET_CMD = []( std::uint64_t x ) -> std::uint32_t { return ( x & 0x0000FFFF ); };
89 constexpr auto PCI_GET_CMD_IO_ACCESS_ENABLED = []( std::uint64_t x ) -> std::uint32_t { return ( x & 0x0001 ); };
90 constexpr auto PCI_GET_CMD_MEMORY_ACCESS_ENABLED = []( std::uint64_t x ) -> std::uint32_t { return ( ( x & 0x0002 ) >> 1 ); };
91 constexpr auto PCI_GET_CMD_ENABLE_MASTERING = []( std::uint64_t x ) -> std::uint32_t { return ( ( x & 0x0004 ) >> 2 ); };
92 constexpr auto PCI_GET_CMD_SPECIAL_CYCLE_MONITORING = []( std::uint64_t x ) -> std::uint32_t { return ( ( x & 0x0008 ) >> 3 ); };
93 constexpr auto PCI_GET_CMD_MEM_WRITE_INVAL_ENABLE = []( std::uint64_t x ) -> std::uint32_t { return ( ( x & 0x0010 ) >> 4 ); };
94 constexpr auto PCI_GET_CMD_PALETTE_SNOOP_ENABLE = []( std::uint64_t x ) -> std::uint32_t { return ( ( x & 0x0020 ) >> 5 ); };
95 constexpr auto PCI_GET_CMD_PARITY_ERROR_RESPONSE = []( std::uint64_t x ) -> std::uint32_t { return ( ( x & 0x0040 ) >> 6 ); };
96 constexpr auto PCI_GET_CMD_WAIT_CYCLE_CONTROL = []( std::uint64_t x ) -> std::uint32_t { return ( ( x & 0x0080 ) >> 7 ); };
97 constexpr auto PCI_GET_CMD_SERR_ENABLE = []( std::uint64_t x ) -> std::uint32_t { return ( ( x & 0x0100 ) >> 8 ); };
98 constexpr auto PCI_GET_CMD_FAST_BACK2BACK_ENABLE = []( std::uint64_t x ) -> std::uint32_t { return ( ( x & 0x0200 ) >> 9 ); };
99 constexpr auto PCI_GET_CMD_LEGACY_INTERRUPT_DISABLE = []( std::uint64_t x ) -> std::uint32_t { return ( ( x & 0x0400 ) >> 10 ); };
100
101
102 //
103 // PCI Config Status Register macros ( 0x6 )
104 //
105 constexpr auto PCI_GET_STATUS( std::uint64_t x ) { return ( ( x & 0xFFFF0000 ) >> 16 ); }
106 constexpr auto PCI_GET_STATUS_66MHZ_CAPABLE( std::uint64_t x ) { return ( ( x & 0x00200000 ) >> 21 ); }
107 constexpr auto PCI_GET_STATUS_UDF_SUPPORTED( std::uint64_t x ) { return ( ( x & 0x00400000 ) >> 22 ); }
108 constexpr auto PCI_GET_STATUS_FAST_BACK2BACK_CAPABLE( std::uint64_t x ) { return ( ( x & 0x00800000 ) >> 23 ); }
109 constexpr auto PCI_GET_STATUS_DATA_PARITY_REPORTED( std::uint64_t x ) { return ( ( x & 0x01000000 ) >> 24 ); }
110 constexpr auto PCI_GET_STATUS_DEVSEL_TIMING( std::uint64_t x ) { return ( ( x & 0x06000000 ) >> 25 ); }
111 constexpr auto PCI_GET_STATUS_SIGNALLED_TARGET_ABORT( std::uint64_t x ) { return ( ( x & 0x08000000 ) >> 27 ); }
112 constexpr auto PCI_GET_STATUS_RECEIVED_TARGET_ABORT( std::uint64_t x ) { return ( ( x & 0x10000000 ) >> 28 ); }
113 constexpr auto PCI_GET_STATUS_RECEIVED_MASTER_ABORT( std::uint64_t x ) { return ( ( x & 0x20000000 ) >> 29 ); }
114 constexpr auto PCI_GET_STATUS_SIGNALLED_SYSTEM_ERROR( std::uint64_t x ) { return ( ( x & 0x40000000 ) >> 30 ); }
115 constexpr auto PCI_GET_STATUS_DETECTED_PARITY_ERROR( std::uint64_t x ) { return ( ( x & 0x80000000 ) >> 31 ); }
116
117 constexpr auto PCI_GET_STATUS_GET_DEVSEL_STRING( std::uint64_t x ) { return ( ( ( ( x & 0x0600 ) == 0x0000 ) ? "fast" :
118 ( ( ( ( x & 0x0600 ) == 0x0200 ) ? "medium" :
119 ( ( ( ( x & 0x0600 ) == 0x0400 ) ? "slow" :
120 ( ( ( ( x & 0x0600 ) == 0x0600 ) ? "reserved" :
121 "unknown" ) ) ) ) ) ) ) ); }
122
123
124 //
125 // PCI BIST/Header Type/Latency Timer/Cache Line Size Register macros ( 0xF/0xE/0xD/0xC )
126 //
127 constexpr auto PCI_GET_BIST( std::uint64_t x ) { return ( ( x & 0xFF000000 ) >> 24 ); }
128 constexpr auto PCI_GET_HEADER_TYPE( std::uint64_t x ) { return ( ( x & 0x00FF0000 ) >> 16 ); }
129 constexpr auto PCI_GET_LATENCY_TIMER( std::uint64_t x ) { return ( ( x & 0x0000FF00 ) >> 8 ); }
130 constexpr auto PCI_GET_CACHE_LINE_SIZE( std::uint64_t x ) { return ( x & 0x000000FF ); }
131
132 constexpr auto PCI_GET_BIST_COMPLETE_CODE( std::uint64_t x ) { return ( x & 0x0F ); }
133 constexpr auto PCI_GET_BIST_INVOKED( std::uint64_t x ) { return ( ( x & 0x40 ) >> 6 ); }
134 constexpr auto PCI_GET_BIST_CAPABLE( std::uint64_t x ) { return ( ( x & 0x80 ) >> 7 ); }
135
136
137 //
138 // PCI Base Address Register macros ( 0x24 - 0x10 )
139 //
140 constexpr auto PCI_GET_BASE_ADDR( std::uint64_t x ) { return ( ( x & 0xFFFFFFF0 ) >> 4 ); }
141 constexpr auto PCI_GET_BASE_ADDR_TYPE( std::uint64_t x ) { return ( x & 0x00000001 ); }
142 constexpr auto PCI_GET_BASE_ADDR_MEM_TYPE( std::uint64_t x ) { return ( ( x & 0x00000006 ) >> 1 ); }
143 constexpr auto PCI_GET_BASE_ADDR_MEM_PREFETCHABLE( std::uint64_t x ) { return ( ( x & 0x00000008 ) >> 3 ); }
144 constexpr auto PCI_GET_BASE_ADDR_MEM_TYPE_STRING( std::uint64_t x ) { return ( ( ( PCI_GET_BASE_ADDR_MEM_TYPE( x ) == 0x0 ) ? "locate anywhere 32-bit addr space" : \
145 ( ( ( PCI_GET_BASE_ADDR_MEM_TYPE( x ) == 0x1 ) ? "locate below 1 Meg" : \
146 ( ( ( PCI_GET_BASE_ADDR_MEM_TYPE( x ) == 0x2 ) ? "locate anywhere 64-bit addr space" : \
147 "reserved" ) ) ) ) ) ); }
148
149 //
150 // PCI Max_Lat/Min_Grant/Interrupt Pin/Interrupt Line Register macros ( 0x3C )
151 //
152 constexpr auto PCI_GET_MAX_LAT( std::uint64_t x ) { return ( ( x & 0xFF000000 ) >> 24 ); }
153 constexpr auto PCI_GET_MIN_GRANT( std::uint64_t x ) { return ( ( x & 0x00FF0000 ) >> 16 ); }
154 constexpr auto PCI_GET_INTR_PIN( std::uint64_t x ) { return ( ( x & 0x0000FF00 ) >> 8 ); }
155 constexpr auto PCI_GET_INTR_LINE( std::uint64_t x ) { return ( x & 0x000000FF ); }
156
157 } // end gen3 namespace
158} // end arc namespace